1. Field of the Invention
This invention relates generally to semiconductor technology and more particularly to semiconductor devices and methods of manufacturing same.
2. Prior Art
Many electrical circuits which are embodied in integrated semiconductor form employ merged transistor structures wherein regions of the semiconductor body provide multiple functions. Typical is the integrated injection logic cell, wherein an injector transistor and a complementary gate transistor have common regions, i.e., the collector of the lateral or injector transistor is interconnected with the base of the gate transistor via a common diffused region, and the base of the injector transistor is similarly interconnected with the emitter of the gate transistor. Embodiments of such structures are found in copending U.S. application Ser. No. 518,445, filed Oct. 29, 1974, now U.S. Pat. 3,962,717 for "COMBINED METHOD FOR FABRICATING OXIDE-ISOLATED VERTICAL BIPOLAR TRANSISTORS AND COMPLEMENTARY OXIDE-ISOLATED LATERAL BIPOLAR TRANSISTORS AND THE RESULTING STRUCTURES, " now U.S. Pat. No. 3,962,717 issued June 8, 1976, assigned to the present assignee.
As disclosed therein, a process for fabricating oxide-isolated vertical bipolar transistors, complementary oxide-isolated lateral bipolar transistors and composite bipolar transistors merging both vertical and lateral bipolar transistors comprises the steps of growing a doped epitaxial layer on a semiconductor substrate, the epitaxial layer having a conductivity type opposite to the cnductivity type of the substrate, forming a groove in the epitaxial layer to surround and define a device region, selectively applying an impurity to the groove to selectively form a guard ring, the impurity having a conductivity type opposite to the conductivity type of the epitaxial layer, forming oxide-isolation regions in the grooves and forming at least one semiconductor device in the device region. In a preferred embodiment in which vertical bipolar transistors and complementary lateral bipolar transistors are merged into an injection logic gate, the step of forming a groove is accomplished by the step of applying a first insulation material in a selected pattern over the epitaxial layer to define oxide-isolation regions and device regions, and by etching those areas in which oxide-isolation regions will be formed and the step of selectively applying an impurity to the grooves is accomplished by an ion implantation technique which allows impurities to be introduced into the bottom portion of the groove but not into the vertical side wall. This provides electrical isolation between the buried layer regions of adjacent devices.
The resulting oxide-isolated structure comprises the semiconductor substrate, an epitaxial layer overlying the substrate and having a conductivity type opposite to that of the substrate, an oxide-isolation region which surrounds and defines a device region, the device region having a guard ring selectively formed at the interface of the oxide-isolation region and the device region, and at least one semiconductor device formed in the device region.
In such semiconductor structures, it is often desirable and advantageous to provide a low doped base region between the collector and the overlying emitter regions in order to achieve a higher gain transistor characteristic and for high speed operation. This area is commonly referred to as the intrinsic or active base region. Further, to improve the current capability of the transistor or to enhance the overall circuit performance by increasing the fan out capability, a low base resistance is desired in the semiconductor base region not juxtaposed between the collector and base transistor regions. This region is commonly referred to as the extrinsic base region. Heretofore, these characteristics have been achieved through the use of selective masking, by driving a heavily-doped emitter region through a heavily-doped base region to interface with a lower doped underlying base region, and by the use of ion-implantation in defining the emitter region. Each of these methods has limitations in adding to process complexity, diffusion control, and/or damage to the semiconductor lattice when applying heavy ion implantation.